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write after read - tradução para árabe
PROBLEMS WITH THE INSTRUCTION PIPELINE IN CENTRAL PROCESSING UNIT (CPU) MICROARCHITECTURES
Pipeline break; Branch hazard; Control hazard; Data hazard; Structural hazard; Pipeline hazard; Hazard (digital circuit); Control hazards; Pipeline flush; RAW conflict; Read after write (Hazard); Write after write (hazard); Write after read (hazard); Write after read
write after read
تسجيل بعد القراءة
RMW
CLASS OF COMPUTER OPERATIONS
RMW; Read modify write; Read-modify-write
ذروة اكتب / عدِّل/ اقرأ فى ذاكرة الوصول العشوائى .
Written off
REDUCTION IN RECOGNIZED VALUE OF AN ENTITY
Write down; Goodwill writedown; Written off; Write-down; Writeoff; Writedown; Writedowns; Totalled; Write off; Tax write-off; Tax writeoff
مشطوبة، مستبعدة
Definição
pipeline break
<architecture> (Or "pipeline stall") The delay caused on a
processor using pipelines when a transfer of control is
taken. Normally when a control-transfer instruction (a
branch, conditional branch, call or trap) is taken, any
following instructions which have been loaded into the
processor's pipeline must be discarded or "flushed" and new
instructions loaded from the branch destination. This
introduces a delay before the processor can resume execution.
"Delayed control-transfer" is a technique used to reduce
this effect.
(1996-10-13)
Wikipédia
Hazard (computer architecture)
In the domain of central processing unit (CPU) design, hazards are problems with the instruction pipeline in CPU microarchitectures when the next instruction cannot execute in the following clock cycle, and can potentially lead to incorrect computation results. Three common types of hazards are data hazards, structural hazards, and control hazards (branching hazards).
There are several methods used to deal with hazards, including pipeline stalls/pipeline bubbling, operand forwarding, and in the case of out-of-order execution, the scoreboarding method and the Tomasulo algorithm.
